1. Field of the Invention
The invention relates to a non-volatile memory device and, more particularly, to an erase method of a non-volatile memory device.
2. Description of Related Art
Generally, semiconductor memory devices to store data are classified into volatile memory devices such as DRAM and SRAM, and non-volatile memory devices such as PROM, EPROM, MRAM, FRAM, and flash EEPROM. The volatile memory devices lose their stored data when their power supplies are interrupted, while the non-volatile memory devices continuously hold their stored data even when their power supplies are interrupted. Therefore, non-volatile memory devices such as flash EEPROMs (hereinafter referred to as “flash memory devices”) are widely used as data storages for various applications such as computer systems whose power supplies have a possibility to be interrupted.
A NAND flash memory device includes electrically erasable and programmable read-only memory cells, which are called “flash EEPROM cells”. A typical flash EEPROM cell has a cell transistor that includes a first conduction-type (e.g., P-type) semiconductor substrate (or bulk), second conduction-type (e.g., N-type) source and drain regions spaced apart from each other, a floating gate disposed over a channel region between the source and drain regions to store charges, and a control gate disposed on the floating gate. An array of a NAND flash memory device having such a cell transistor is illustrated in FIG. 1. The array of the NAND flash memory device includes a plurality of cell strings (or NAND strings). In FIG. 1, only one of the cell strings is shown.
A cell string includes a string select transistor SST being a first select transistor, a ground select transistor GST being a second select transistor, and a plurality of memory cells MC0-MCm being serially coupled between the select transistors SST and GST. The string select transistor SST has a drain coupled to a corresponding bitline BL and a gate connected to a string select line SSL. The ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. Memory cells MCm-MC0 (m=31) are serially coupled between a source of the string select transistor SSL and a drain of the ground select transistor GSL. The memory cells MCm-MC0 are connected to corresponding wordlines WLm-WL0, respectively. A bitline BL is connected to a page buffer PB.
As being well known to those skilled in the art, a group of cell strings illustrated in FIG. 1 is called a memory block. In a NAND flash memory device, program and read operations are performed per page and an erase operation is performed per block. Generally, an erase procedure is followed by a program operation to erase memory cells. As illustrated in FIG. 2, an erase procedure comprises performing an erase operation (S10) and performing an erase-verify operation (S20). In the step S10, memory cells of a memory block are erased at the same time. The memory cells are erased by, for example, applying a voltage of 0V to wordlines WL0-WL31 and a high voltage (e.g., 20V) to a substrate (or bulk). That is, electrons of floating gates are emitted to a substrate to make a threshold voltage lower to an erase threshold voltage of −1V˜−3V. In the step S20, it is judged weather threshold voltages of the erased memory cells are lower than erase threshold voltage (or target threshold voltage; for example, −1V). The steps S10 and S20 are repeated within the number of determined erase cycles until all memory cells are sufficiently erased.
A conventional erase-verify operation will now be described with reference to a timing diagram of FIG. 3. Roughly, a conventional erase-verify operation includes a bitline discharge period T0, a bitline precharge period T1, a sense period T2, and a recovery period T3. In the bitline discharge period T0, a voltage of a bitline BL is discharged to a ground voltage through a page buffer PB shown in FIG. 1. In the bitline precharge period T1, the bitline BL is precharged to a predetermined voltage through the page buffer PB. In the sense period T2, it is sensed whether cell current flows through a cell string. For example, during the sense period, sensing current is supplied from the page buffer PB to the bitline BL, while a voltage of 0V is applied to all wordlines WL0-WL31. At this time, a read voltage Vread is applied to a string select line SSL and a ground select line GSL. According to the above bias condition, sensing current supplied to the bitline BL is discharged to a common source line CSL through a cell string when threshold voltages of all memory cells reach or are lower than an erase threshold voltage. The page buffer PB senses a voltage level of a bitline BL and latches data ‘1’, as a sensing result, indicating that all memory cells of a cell string are sufficiently erased. Latch values corresponding to cell strings of a memory block are transmitted to a pass/fail check circuit (see FIG. 4). In the recovery period T3, voltages of wordlines, bitlines, and select lines are initialized to 0V.
The above-described erase-verify method is disclosed in U.S. Pat. No. 6,009,014 entitled “ERASE VERIFY SCHEME FOR NAND FLASH”.
As an operating voltage (or power supply voltage) drops, conventional erase-verify methods encounter the following problems. As described above, a sensing operation is performed while a voltage of 0V is applied to control gates of all memory cells of a cell string (or all wordlines). According to the above erase-verify method, although a memory cell is judged as an erased cell during a normal read operation, a cell string having such a memory cell (e.g., a weak well which may be produced in a process) causes an erase failure during an erase-verify operation. That is, in case of a low voltage NAND flash memory device using the foregoing erase-verify method, a low voltage margin becomes poor and thus a cell judged as an erase cell during a normal read operation causes an erase failure during an erase-verify operation.